This invention relates to a data transmitter for transmitting parallel data; and, more particularly, the invention relates to a data transmitter suited for transmitting data at high speeds in a memory system.
In the devices for transmitting data at high speeds, the data propagation delay time through the transmission paths is increasing to such a degree that is no longer negligible relative to the data transmission period. A device that must transmit data at high speeds can be represented by a memory system which comprises a microprocessor (MPU), a memory controller LSI and a plurality of memory modules, and is used in a personal computer. Each memory module mounts a plurality of synchronous DRAMs (SDRAMs) which are memory chips. When data is to be read out in this memory system, the SDRAM on the memory module works as a driver for transmitting data, and the memory controller works as a receiver for receiving the data.
The memories at the same positions on the memory modules share a data signal wiring on a bus. In this case, the wiring length differs between a memory module and the memory controller LSI when the data is read out from the SDRAM on a memory module closer to the memory controller LSI and from the SDRAM on a memory module more distant from the memory controller LSI. When the memory controller LSI reads out data from the SDRAM of the distant memory module, therefore, the arrival of data is delayed by a difference in the propagation delay time between the two memory modules as compared to when the data is read out from the SDRAM of the closer memory module.
Thus, when the receiver receives the data by using a reference signal of a predetermined timing relative to the signals arriving at timings that differ depending on the positions of the modules, the effective time of the data decreases making it no longer possible to maintain a setup time for receiving data and a holding time.
This problem can be solved by, for example, a method disclosed in Japanese Patent Laid-Open No. 157030/1991. According to this method, the driver that produces data sends, together with data signals, reference signals for receiving the data to absorb differences in the transmission delay time.
FIGS. 3A and 3B schematically illustrate typical memory modules having a data bit width of 64 bits as used in the above memory system, wherein FIG. 3A shows a memory module mounting four SDRAMs of x 16 bit output, and FIG. 3B shows a memory module mounting 16 SDRAMs of x 4 bit output. Here, FIG. 3B shows only one surface of the memory module.
The two memory modules of FIGS. 3A and 3B employ a uniform pin arrangement, and have data signals DQi (i=0 to 63), signals CLKj (j=0 to 3) used as a reference for writing data from the memory controller LSI into the SDRAM, and reference signals DQSj (j=0 to 3) used for reading data from the SDRAM into the memory controller LSI, each of which is four in number. The data signal DQi consists of 64 bits and, hence, the reference signals CLKj and DQSj each receive 16 data signals as a reference.
Hereinafter, the reference signals CLK0 and DQS0 are used to write and read data signals DQ0 to DQ15 as a reference, respectively; the reference signals CLK1 and DQS1 are used to write and read data signals DQ16 to DQ31 as a reference, respectively; the reference signals CLK2 and DQS2 are used to write and read data signals DQ32 to DQ47 as a reference, respectively; and reference signals CLK3 and DQS3 are used to write and read data signals DQ48 to DQ63 as a reference, respectively.
Here, in the memory module of FIG. 3A, four SDRAMs are mounted and, hence, the reference signals and the corresponding 16 data signals are connected to the same SDRAM. in the memory module 6f FIG. 3B, on the other hand, 16 SDRAMs are mounted and, hence, the reference signals CLK1 are branched into four areas on the memory module to distribute signals to each of the SDRAMs. The reference signal DQSj is representatively used as a reference for receiving data of four chips from an SDRAM.
FIG. 4A illustrates, in a simplified manner, an example of a driver DRV on a module which transmits signals while bringing the data signals DQi (i=A, B, C) into phase with the reference signals CLK for receiving the data, and the receiver RCV receives the data by delaying the phase of the reference signals CLK by one-half period (T/2). FIG. 4B is a timing diagram of the relevant signals.
Here, reference numerals 401, 402 and 403 denote flip-flops for determining the output phases of the signals DQA, DQB, DQC, reference numerals 411, 412, 413 and 414 denote output buffers for the signals DQA, DQB, DQC, CLK, and reference numerals 421, 422, 423 and 424 denote signal wirings for connecting the driver to the receiver and comprise a bus between the memory module and the memory controller LSI. Reference numerals 431, 432, 433 and 434 denote input buffers for the signals in the receiver, and reference numerals 441, 442 and 443 denote flip-flops for receiving the transmitted data.
The driver having data signals DQi (i=A, B, C) and reference signals CLK to be transmitted may be in the form of, for example, a single chip as shown in FIG. 3A or it may be constituted by a plurality of different chips like signals DQS in FIG. 3B. In either case, the difference in the length of the transmission paths to the memory modules can be absorbed by transmitting reference signals for receiving data simultaneously with the transmission of data signals as disclosed in Japanese Patent Laid-Open No. 157030/1991.
For this purpose, however, the wirings 421 to 424 for the data signals and reference signals must have an equal length, and their loads must be equalized. If the wirings having an equal length and an equal load have been realized between the data signals and the reference signals that are transmitted in parallel, the relationship of phase between the data signals DQA to DQC in the flip-flops 401 to 403 and the clock signals CLK in the driver DRV will be maintained so as to be relatively the same even after they have passed through the input buffers 431 to 434 in the receiver RCV as shown in the timing diagram of FIG. 4B.
Therefore, the reference signals and the data signals transmitted from the driver at the same timings arrive at the receiver all at the same timing irrespective of the wirings 421 to 424 between the driver and the receiver, i.e., irrespective of the lengths of the transmission paths between the memory controller LSI and the memory module. When the receiver receives the data using the reference signals, the setup time (tDS) 451 and the holding time (tDH) 452 can be maintained to a sufficient degree.
As another example, Japanese Patent Laid-open No. 75594/1993 discloses a parallel bit synchronizing system comprising a training data generating circuit and a selector for changing the normal data and the training data over to each other in response to a training mode signal on the data transmission side, a bit phase synchronizing circuit that operates in the training mode to automatically synchronize the phase among the bit data, and an inter-bit phase synchronizing circuit connected to the bit phase synchronizing circuit to automatically synchronize the phases among the bit data on the data receiving side.
According to the above first example in which the driver transmits the reference signals together with the data signals, however, there exists a region 501 on the printed board or on the memory module board where it is not allowed to lay wiring, as shown in FIG. 5A. Therefore, it often becomes difficult to maintain an equal length of the wirings for the reference signals CLK and the data signals DQA to DQC. Even if the wirings of an equal length could be realized, the presence of parasitic capacitance due to the wirings running in parallel with other wirings or crossing other wirings and the dispersion of processes among the chips make it difficult to uniformalize the characteristics of the input/output buffers and, hence, make it difficult to equalize the loads among the wirings. In such a case, the propagation delay time differs among the signal wirings, and even the signals transmitted in phase from the driver DRV do not necessarily arrive at the receiver RCV simultaneously.
In the example shown in FIG. 5A, the wiring 521 of the data signal DQA is longer than the other wirings, and a parasitic capacitance 522 is formed, causing the propagation delay time of the signal DQA to increase. As for the data signal DQC, further, the input capacity of the input buffer 533 in the receiver RCV is smaller than that of input buffers for other signals. In such a case, as shown in the timing diagram of FIG. 5B, the signal DQA arrives at the receiver at a delayed timing and the signal DQC arrives at the receiver at an advanced timing relative to the timing at which the signal DQB and the signal CLK arrive at the receiver. As a result, both the setup time (tDS) 551 and the holding time (tDH) 552 are shortened.
As shown in FIG. 3B, further, when the data signals DQi and reference signals DQSJ are formed by different chips, there will be an added dispersion to the delay times of the output buffers.
In the high-speed data transmission of a short period, the difference in the propagation delay time among the parallel data become no longer negligible, creating a problem in that the setup time for receiving the data and the holding time are not maintained, and the data is not normally transmitted.
According to the second example for synchronizing the parallel bits, the data path differs between the training data generating circuit and the data generating circuit during normal operation. Therefore, even if the synchronism is established among the data signals, clock signals and data signals relying upon the training, a difference in the delay time occurs during the normal transmission of data.
The object of this invention is to provide a data transmitter which is capable of transmitting parallel data without error even when there is a difference in the lengths of paths among the parallel data wirings and in the load capacities inclusive of parasitic elements in the high-speed data transmission over a short period, overcoming the above problem.
In order to accomplish the above object according to this invention, the receiver for receiving parallel data is provided with a simultaneous arrival judging circuit that compares the phases of part or all of the received data. There is further provided a timing adjusting mechanism for adjusting the phases at a point of receiving data in the receiver based on the result of judgement of the simultaneous arrival judging circuit, so that the data signals simultaneously arrive at the receiver, thereby to maintain a setup time for receiving the data and a holding time. Here, the signals used as a reference for receiving the data may be transmitted from the driver to the receiver together with the data signals, or reference signals in the receiver may be used.
Here, the timing adjusting mechanism may be a circuit for varying the phases of the data or of the reference signals, or it may be a circuit for varying the driving force of the output buffers of the driver.
Further, in order to absorb the difference in the delay time among the signals dependent upon a sequence of data, the timing adjusting mechanism is so constituted as to vary the timing depending even upon the time series of the data bits that are transmitted.
Further, the timing adjusting mechanism can be provided in the driver chip, in the receiver chip, or in a chip formed between the driver chip and the receiver chip, and it is different from either the driver or the receiver.
In particular, parallel data of two or more bits transmitted by the driver and received by the receiver may be output from a plurality of different driver chips. As a reference signal for judging the simultaneous arrival at the receiver, it is desired to use a signal which is common among the above plurality of different driver chips.